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HY51V(S)65163HG/HGL
4M x 16Bit EDO DRAM
PRELIMINARY
DESCRIPTION
This familiy is a 64Mbit dynamic RAM organized 4,194,304 x 16bit configuration with Extended Data Out mode CMOS DRAMs. Extended data out mode is a kind of page mode which is useful for the read operation. The advanced circuit and process allow this device to achieve high performance and low power dissipation. Features are access time(45ns or 50ns) and refresh cycle(4K ref ) and power consumption (Normal or low power with self refresh). Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to achieve high speed access and high reliability
FEATURES
* * * * * Extended data out operation Read-modify-write capability Multi-bit parallel test capability LVTTL(3.3V) compatible inputs and outputs /RAS only, CAS-before-/RAS, Hidden and self refresh(L-version) capability * * * JEDEC standard pinout 50pin plastic SOJ/TSOP-II(400mil) Single power supply of 3.3V +/- 10% Battery back up operation(L-version)
*
Fast access time and cycle time
Part No HY51V(S)65163HG/HGL-45 HY51V(S)65163HG/HGL-5 HY51V(S)65163HG/HGL-6 tRAC 45ns 50ns 60ns tAA 23ns 25ns 30ns tCAC 12ns 13ns 15ns tRC 74ns 84ns 104ns tHPC 17ns 20ns 25ns
*
Power dissipation
45ns Active Standby 468mW 50ns 432mW 60ns 396mW
*
Refresh cycle
Part No HY51V65163HG* HY51V65163HGL* Ref 4K Ref 4K Ref Normal 64ms 128ms L-part
1.8mW(CMOS level Max) 0.72mW (L-version : Max)
* : /RAS only, CBR and hidden refresh
ODERING INFORMATION
Part Number HY51V(S)65163HG/HG(L)J-45 HY51V(S)65163HG/HG(L)J-5 HY51V(S)65163HG/HG(L)J-6 HY51V(S)65163HG/HG(L)T-45 HY51V(S)65163HG/HG(L)T-5 HY51V(S)65163HG/HG(L)T-6
(S) : Self refresh, (L) : Low power
Access Time 45ns 50ns 60ns 45ns 50ns 60ns
Package
400mil 50pin SOJ
400mil 50pin TSOP-II
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.0.1/Apr.01
HY51V(S)65163HG/HGL
PIN CONFIGURATION
VCC IO0 IO1 IO2 IO3 VCC IO4 IO5 IO6 IO7 NC VCC /WE /RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 VSS 49 48 47 46 IO15 IO14 IO13 IO12
45 VSS 44 43 42 41 40 39 38 IO11 IO10 IO9 IO8 NC VSS /LCAS
37 /UCAS 36 35 /OE NC
34 NC 33 32 31 30 29 28 27 26 NC A11 A10 A9 A8 A7 A6 VSS
50 Pin Plastic SOJ / TSOP-II
PIN DESCRIPTION
Pin /RAS /UCAS, /LCAS /WE /OE A0-A11 A0-A11 I/O 0- I/O15 Vcc Vss NC Function Row Address Strobe Column Address Strobe Write Enable Output Enable Address Inputs Refresh Address Inputs Data Input / Output Power (3.3V) Ground No connection
Rev.0.1/Apr.01
2
HY51V(S)65163HG/HGL
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to Vss Voltage on Vcc relative to Vss Short Circuit Output Current Power Dissipation Symbol TA TSTG VT Vcc IOUT PT Rating 0 ~ 70 -55 ~ 125 -0.5 ~ Vcc + 0.5 (Max 4.6V) -0.5 ~ 4.6 50 1 Unit
o o
C C
V V mA W
Note : Operation at above absolute maximum rating can adversely affect device reliability.
Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC)
Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Symbol Vcc Vss VIH VIL Min 3.0 0 2.0 -0.3 Typ. 3.3 0 Max 3.6 0 Vcc + 0.3 0.8 Unit V V V V Note 1,2 2 1 1
Note : All voltages are referenced to Vss 1. 6.0V at pulse width 10ns which is measured at Vcc 2. -0.1V at pulse width 10ns which is measured at Vss
Rev.0.1/Apr.01
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HY51V(S)65163HG/HGL
DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70C)
Symbol VOH Output Level Output Level voltage(Iout= -2mA) Output Level Output Level voltage(Iout=2mA)
45ns ICC1
Parameter
Min
2.4
Max
Vcc
Unit
V
Note
VOL
0 -
0.4 130 120 110
V
Operating current ( tRC = tRC min)
50ns 60ns
mA
1, 2
ICC2
Standby current (TTL interface) Power supply standby current (/RAS, /UCAS,/LCAS=VIH, Dout = High-Z)
45ns
-
1
mA
-
130 120 110 100 90 80 0.5 200 130 120 110 350 uA 4, 5 mA mA uA 4 mA 1, 3 mA 2
ICC3
/RAS only refresh current (tRC= tRC min)
50ns 60ns 45ns
ICC4
Extended data out page mode current (/RAS=VIL, /CAS, Address cycling : tHPC=tHPC min)
50ns 60ns
CMOS interface ( /RAS, /UCAS, /LCAS >= Vcc-0.2V, Dout = High-Z) ICC5 Standby current ( L-version)
45ns ICC6
-
/CAS-before-/RAS refresh current (tRC=tRC min)
50ns 60ns
ICC7
Battery back up operating current (standby with CBR) (tRC=31.25us, tRAS=300ns, Dout=High-Z) Standby current (CMOS) Power supply standby current /RAS=VIH, /UCAS./LCAS=VIL, Dout=Enable) Self refresh current (/RAS, /UCAS, /LCAS <=0.2V, Dout=High-Z) Input leakage current, Any input (0V<= Vin<=Vcc) Output leakage current, (Dout is disabled, 0V<= Vout<=Vcc)
ICC8
-
5
mA
1
ICC9 II(L) IO(L)
-5 -5
350 5 5
uA uA uA
5
Note : 1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition 2. Address can be changed once or less while RAS=VIL 3. Measured with one sequential address change per EDO cycle, tHPC 4. VIH>=Vcc-0.2V, 0V<=VIL<=0.2V 5. L-Version
Rev.0.1/Apr.01
4
HY51V(S)65163HG/HGL
CAPACITANCE (Vcc=3.3V +/-10%, TA=25C)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Min. Max 5 5 7 Unit pF pF pF Note 1 1 1, 2
Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /RAS, /UCAS and /LCAS = VIH to disable Dout
AC CHARACTERISTICS
Test Condition * *
(Vcc=3.3V +/-10%, TA=0~70C, Note 1, 2, 19,20)
*
Input rise and fall times = 2ns Input level : VIL/VIH = 0.0 / 0.3V Input timing reference level : VIL/VIH = 0.8/2.0V
* *
Output timing reference level : VOL/VOH=0.8/0.2V Output load : 1 TTL gate + CL (100pF) including scope and jig
Read, Write, Read-modify-Write and Refresh Cycles
-45 Parameter Random read or write cycle time /RAS precharge time /CAS precharge time /RAS pulse width /CAS pulse width Row address set-up time Row address hold time Column address set-up time Column address hold time /RAS to /CAS delay time /RAS to Column address delay time /RAS hold time /CAS hold time /CAS to /RAS precharge time Symbol Min tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP 74 25 7 45 7 0 7 0 7 11 9 12 38 5 Max 10,000 10,000 33 22 Min 84 30 8 50 8 0 8 0 8 12 10 13 40 5 Max 10,000 10,000 37 25 Min 104 40 10 60 10 0 10 0 10 14 12 15 42 5 Max 10,000 10,000 45 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
22 21 21 3 4 24
-50
-60
Unit Note
Rev.0.1/Apr.01
5
HY51V(S)65163HG/HGL
- continued -45 Parameter /OE to Din delay time /OE delay time from Din /CAS delay time from Din Transition time ( Rise and Fall) Refresh period tREF Refresh period (L-version) 128 128 128 ms 4K Ref. Symbol Min tODD tDZO tDZC tT 12 0 0 2 Max 50 64 Min 13 0 0 2 Max 50 64 Min 15 0 0 2 Max 50 64 ns ns ns ns ms 5 6 6 7 4K Ref. -50 -60
Unit Note
Read Cycles
-45 Parameter Access time from /RAS Access time from /CAS Access time from column address Access time from /OE Read command set-up time Read command hold time to /CAS Read command hold time to /RAS Column address to /RAS lead time Column address to /CAS lead time Output buffer turn off delay time from /CAS Output buffer turn off delay time from /OE /CAS to Din delay time /RAS to Din delay time /WE to Din delay time Output buffer turn off delay time from /RAS Output buffer turn off delay time from /WE Output data hold time Output data hold time from /RAS Read command hold time from /RAS Output data hold time from /OE /CAS to output in low-Z Symbol Min tRAC tCAC tAA tOAC tRCS
tRCH
-50 Max 45 12 23 12 12 12 12 12 Min 0 0 0 25 15 13 13 13 3 3 50 3 0 Max 50 13 25 13 13 13 13 13 Min 0 0 0 30 18 15 15 15 3 3 60 3 0
-60
Unit Note
Max 60 15 30 15 15 15 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13,26 13 26 26 13,26 13 5 8, 9 9,10,17 9,11,17 9 21 12,22 12
0 0 0 23 15 12 12 12 3 3 45 3 0
tRRH tRAL tCAL tOFF tOEZ
tCDD
tRDD tWDD tOFR tWEZ tOH
tOHR
tRCHR tOHO
tCLZ
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6
HY51V(S)65163HG/HGL
Write Cycles
-45 Parameter Write command set-up time Write command hold time Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Symbol Min tWCS tWCH tWP tRWL tCWL
tDS tDH
-50 Max Min 0 8 8 13 8 0 8 Max Min 0 10 10 15 10 0 10
-60
Unit Note
Max ns ns ns ns ns ns ns 23 15, 23 15, 23 14,21 21
0 7 7 12 7 0 7
Read-Modify-Write Cycles
-45 Parameter Read-modify-write cycle time /RAS to /WE delay time /CAS to /WE delay time Column address to /WE delay time /OE hold time from /WE Symbol Min tRWC tRWD tCWD tAWD tOEH 101 63 30 40 12 Max Min 116 67 30 42 13 Max Min 140 79 34 49 15 Max ns ns ns ns ns 14 14 14 -50 -60
Unit Note
Refresh cycles
-45 Parameter /CAS set-up time ( /CAS-before-/RAS Refresh Cycle) /CAS hold time ( /CAS-before-/RAS Refresh Cycle) /WE set-up time ( /CAS-before-/RAS Refresh Cycle) /WE hold time ( /CAS-before-/RAS Refresh Cycle) /RAS precharge to /CAS hold time ( /CAS-before-/RAS Refresh Cycle) Symbol Min tCSR 5 Max Min 5 Max Min 5 Max ns 21 -50 -60
Unit Note
tCHR
7
-
8
-
10
-
ns
22
tWRP
0
-
0
-
0
-
ns
tWRH
7
-
8
-
10
-
ns
tRPC
5
-
5
-
5
-
ns
21
Rev.0.1/Apr.01
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HY51V(S)65163HG/HGL
Extended Data Out Mode Cycles
-45 Parameter EDO page mode cyle time Write pulse width during /CAS precharge EDO mode /RAS pulse width Access time from /CAS precharge /RAS hold time from /CAS precharge /CAS hold time referred /OE /CAS to /OE set-up time Read command hold time from /CAS precharge Output data hold time from /CAS low /OE precharge time Symbol Min tHPC
tWPE
-50 Max 100K 28 Min 20 8 28 8 5 28 3 8 Max 100K 28 Min 25 10 35 10 5 35 3 10
-60
Unit Note
Max 100K 35 ns ns ns ns ns ns ns ns ns ns 9,27 16 9,17,22 25
17 7 26 7 5 26 3 7
tRASP
tACP tRHCP
tCOL
tCOP
tRCHP
tDOH tOEP
EDO Page Mode Read-Modify-Write Cycle
-45 Parameter EDO read-modify-write cycle time EDO page mode read-modify-write cycle /CAS precharge to /WE delay time Symbol Min tHPRWC
tCPW
-50 Max Min 57 45 Max Min 68 54
-60
Unit Note
Max ns ns 14,22
57 45
Self Refresh Cycle (L-Version)
-45 Parameter /RAS pulse width ( self refresh) /RAS precharge time ( self refresh) /CAS hold time ( self refresh) Symbol Min tRASS
tRPS tCHS
-50 Max Min 100 90 -50 Max Min 100 110 -50
-60
Unit Note
Max us ns ns 31 31 23
100 90 -50
Rev 0.1 / Apr. 01
HY51V(S)65163HG/HGL
Notes :
1. AC measurements assume tT = 2ns 2. AC initial pause of 200us is required after power up followed by a minimum of eight initialization cycles ( any combination of cycles containing /RAS-only refresh or /CAS-before-/RAS refresh) 3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 5. Either tODD or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, also transition times are measured between VIH(min) and VIL(max) 8. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown 9. Measured with a load circuit equivalent to 1 TTL loads and 100pF. 10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max) 11. Assumes that tRAD>=tRAD(max) and tRCD + tCAC(max) <= tRAD + tAA(max) 12. Either tRCH of tRRH must be satified for a read cycles 13. tOFF(max), tOEZ(max), tOFR(max) and tWEZ(max) define the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels 14 tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle : If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell : if neither of the above sets of conditions is satified, the condition of the data out (at access time) is indeterminate. 15. tDS and tDH are refered to /UCAS and /LCAS leading edge in early write cycles and to /WE leading edge in delayed write or read-modify-write cycles 16. tRASP defineds /RAS pulse width in extended data out mode cycles 17. Access time is determined by the longest among tAA, tCAC and tACP 18 In delaying write or read-modify-write cycles, /OE must disable output buffer prior to applying data to the device.
Rev 0.1 / Apr. 01
HY51V(S)65163HG/HGL
19. When output buffers are enabled once, sustain the low impedence state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large Vcc/Vss line noise, which causes to degrade VIH min / VIL max level 20. When both /UCAS and /LCAS go low at the same time, all 16 bit data are written into the device. /UCAS and /LCAS cannot be staggered within the same write / read cycles 21. tASC, tCAH, tRCS, tWCS, tWCH, tCSR and tRPC are determined by the earlier falling edge of /UCAS or /LCAS 22. tCRP, tCHR, tRCH,tACP and tCPW are determined by the later rising edge of /UCAS or /LCAS 23. tCWL, tDH, tDS and tCHS should be satified by the both /UCAS and /LCAS 24. tCP is determined by the time that both /UCAS and /LCAS are high 25. tHPC(min) can be achieved during a series of EDO mode early write cycles or EDO mode read cycels If both write and read operation are mixed in a EDO mode, /RAS cycle[EDO mode mix cycle (1)(2)] minimum value of /CAS cycle tHPC[tCAS + tCP + 2tT] become greater than the specified tHPC(min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2) 26. Data output turns off and becomes high impedance from later rising edge of /RAS and /CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of /RAS and /CAS between tOHR and tOH and between tOFR and tOFF 27. tDOH defines the time at which the output level go cross, VOL=0.8V, VOH=2.0V of output timing reference level. 28. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64ms period on the condition a) and b) below a) Enter self refresh mode within 15.6us after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6us after exiting from self refresh mode 29. In case of entering from /RAS-only-refresh, It is necessary to execute CBR refresh before and after self refresh mode according as note 28 30. For L-version, It is available to apply each 128ms and 31.2us instead of 64ms and 15.6us at note 28 31. At tRASS > 100us, self refresh mode is activated, and not active at tRASS < 10us, It is undefined within the range of 10us < tRASS < 100us. For tRASS > 10us, It is necessary to satify tRPS 32. XXX : H or L [ H : VIH(min) <= VIN <=VIH(max), L : VIH(min) <=VIN <=VIH(max)] ///// : Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL
Rev 0.1 / Apr. 01
HY51V(S)65163HG/HGL
PACKAGE INFORMATION
400mil 50pin TSOP- II Dimension
Unit: mm
20.95 MIN 21.35 MAX 0 ~ 5 deg. 0.40 MIN 0.60 MAX
1.20 MAX
0.145 0.125 0.80
0.30 0.28
0.10 0.08
0.80
0.08 MIN 0.18 MAX
0.10
Dimension including the plating thickness Base material dimension
Rev.0.1/Apr.01
0.68
1.15 MAX
11.56 MIN
0.05 0.04
11.96 MAX
10.16
11

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